JTAG is the name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture for test access ports (TAP) used for testing printed circuit boards (PCB) and microprocessors. The acronym JTAG stands for the Joint Test Action Group, the name of the organization of individuals that developed the IEEE 1149.1 standard.
The functionality offered by JTAG is that of providing debug access and boundary scan testing to and of PCBs and microprocessors. Debug Access is used by debugger tools to access the internals of a chip, thereby making its resources and functionality available and modifiable, e.g. registers, memories and the system state. Thus, debug access may be used to test the functioning of the chip itself. Boundary Scan testing is used by hardware test tools to test the physical connection of a chip to other devices on a printed circuit board (PCB). Thus, boundary scan testing may be used to test for proper electrical connections between the chip and other devices.
The debug function may in some cases utilize one TAP, while the boundary scan function utilizes another TAP. However, this may necessitate the use of an extra pin above the minimum required by the JTAG standard, which may be undesirable in some scenarios.
In some instances, both a boundary scan functional TAP and a debug functional TAP can be connected in series. However, this may result in increased latency during boundary scan testing, which may be undesirable.
Therefore, further development in hardware implementing JTAG interfaces is needed.